The E ect of Spot Defects on the Parametric Yield ofLong

The eeect of non-catastrophic (or soft) defects (i.e., neither short nor open) on long interconnection lines is analyzed and an estimate is derived for the frequency-dependent critical area for such lines. The analysis is based on a transmission-line model of interconnection lines, and the reeections caused by the defect are taken into account. This analysis results in an estimated prediction of the parametric yield, and a practical recommendation for a better jog insertion in VLSI routing. 1 Parametric Yield In conventional (catastrophic) yield prediction, the main question is: `How many fault-free chips will be manufactured?' whereas for parametric yield prediction the question is`How many chips will have an acceptable performance?'. The term \acceptable performance" may have diierent interpretations, e.g., frequency, power consumption, MTTF, etc. We will focus in this paper on the frequency interpretation, that is: we will try to answer the question: How many chips will be operational at a desired frequency in the presence of spot defects (assuming a known defect distribution)? In this manuscript we restrict our discussion to interconnection lines. In most previous publications (e.g., 13], 14], 15]) it was assumed that signiicant para-metric yield loss can only be caused by global process faults (e.g., mask misalignment and line width variations), while local process defects (pinholes, missing/extra metal) can only result in catastrophic faults. A detailed survey of existing methods in parametric yield analysis can be found in 17]. A preliminary analysis of the eeect of spot defects on the circuit performance was made in 7], but the model used there does not take into account the eeect of the discontinuities in the transmission lines caused by spot defects; hence the resulting reeections are not considered. Such reeections, which may have been negligible when CPU clock frequencies were below 100Mhz, have become more crucial with recent progress in technology and higher processing rates. Our goal here is to investigate the eeect of local process defects on the parametric yield of metal lines by analyzing the increase in the (signal propagation) delay of such lines due to spot defects. We extend the well-known notion of critical area and estimate the delay-increase-dependent yield Y (), which is deened as the percentage of chips that will On temporary leave from